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• W2056992005 abstract "A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (/spl les/550/spl deg/C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH/sub 3/ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm/sup 2//V-s, ON/OFF current ratio of over 10/sup 7/, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate." @default.
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• W2056992005 date "1996-11-01" @default.
• W2056992005 modified "2023-10-18" @default.
• W2056992005 title "Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors" @default.
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• W2056992005 doi "https://doi.org/10.1109/55.541762" @default.
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