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• W2057114406 abstract "Multiple cores interact through a complex shared-memory hierarchy that must satisfy coherence and consistency requirements. As the number of cores grows, the design of the memory system becomes more error-prone, since it is more difficult to fulfill shared-memory requirements with the growing number of local memories distributed among cores. That is why a checker must be used to verify if coherence and consistency are satisfied by the design representation (pre-silicon) or by the hardware prototype (post-silicon). In industrial environments, checkers developed for post-silicon verification are often reused at design time, although recent works show that the higher observability of a design representation should be exploited to speed up pre-silicon verification. The literature reports many checkers, yet direct comparisons between them are rare. To bridge that gap, we evaluated four distinct classes of checkers, each under 5000 use-cases scenarios. The results allow us to make the case for on-the-fly checking as the most efficient approach for pre-silicon verification, since it speeds up analysis by at least one order of magnitude as compared to conventional inference-based checkers. Besides, we found out that the use of multiple scoreboards doubles the probability of finding an error as compared to a unified scoreboard." @default.
• W2057114406 created "2016-06-24" @default.
• W2057114406 creator A5013441804 @default.
• W2057114406 creator A5033216070 @default.
• W2057114406 date "2013-12-01" @default.
• W2057114406 modified "2023-09-26" @default.
• W2057114406 title "Pre-silicon verification of multiprocessor SoCs: The case for on-the-fly coherence/consistency checking" @default.
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• W2057114406 doi "https://doi.org/10.1109/icecs.2013.6815546" @default.
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