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- W2057187623 abstract "VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log2 n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log2 n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log2 n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor’s pipeline and other architectures is discussed." @default.
- W2057187623 created "2016-06-24" @default.
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- W2057187623 date "2014-07-01" @default.
- W2057187623 modified "2023-10-09" @default.
- W2057187623 title "A low energy dual-mode adder" @default.
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- W2057187623 doi "https://doi.org/10.1016/j.compeleceng.2014.04.012" @default.
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