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- W2058059450 abstract "In hardware implementation, there are different architectures that can represent the same algorithm into hardware. The different architectures are usually caused by using different number representations. In this work, two hardware architectures of optical flow constraint equation of Horn and Schunck (OFCE-HS) are presented and compared. The first architecture (OFCE-HS MZ) is previous work using full integer number to represent the architecture. The second architecture (OFCE-HS RH) is our work using combination between integer and fraction number to represent the architecture. Hardware designs of the architectures are performed using Xilinx System Generator through HW-SW co-simulation scheme. As a result, our proposed work has better performance compared to the previous work. It has the ability to reduce noise as well as hardware resources." @default.
- W2058059450 created "2016-06-24" @default.
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- W2058059450 date "2012-06-01" @default.
- W2058059450 modified "2023-09-26" @default.
- W2058059450 title "FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck" @default.
- W2058059450 cites W2019193226 @default.
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- W2058059450 doi "https://doi.org/10.1109/icias.2012.6306121" @default.
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