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• W2058858903 abstract "We present an 8.0-Gb/s HyperTransport source-synchronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by incorporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20-296 MHz (measured with 0.2 UI <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>pp</sub> input jitter) and 0.90-1.50 ps output rms jitter by implementing an extended bang-bang phase detector for additional phase-error magnitude information and flexible bang-bang control of a current-starved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as well as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal compatibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy efficiency of 11.8 pJ/bit. This reflects a 4.9% increase in HyperTransport power consumption and only 0.3% increase in total processor target power relative to 45-nm operation at 6.4 Gb/s." @default.
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• W2058858903 date "2012-11-01" @default.
• W2058858903 modified "2023-09-27" @default.
• W2058858903 title "An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors" @default.
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• W2058858903 doi "https://doi.org/10.1109/jssc.2012.2211697" @default.
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