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- W2058967098 abstract "Abstract The multiple busses network is attractive for interconnecting processors to memory modules in a multiprocessor system. The use of this network requires an M -musers B -servers arbiter. In this paper we show several designs for such an arbiter with a round-robin policy. The iterative design is simple but relatively slow and does not use all the possibilities of integration. A network with one level of lookahead is faster and more integrated. To increase even more the speed of arbitration a design with two levels of lookahead is proposed. This network can be used effectively for up to 16 processors, memory modules and busses." @default.
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- W2058967098 date "1982-08-01" @default.
- W2058967098 modified "2023-10-16" @default.
- W2058967098 title "M-users B-servers arbiter for multiple-busses multiprocessors" @default.
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- W2058967098 doi "https://doi.org/10.1016/0165-6074(82)90117-x" @default.
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