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- W2059092162 abstract "This paper illustrates how the synchronous programming language Esterel [3] can be used to design and verify both hardware and software. Also illustrates that power of combining these two complementary technologies for the design and verification of embedded systems. Finally we show how the Esterel technique fits into a conventional system level design flow based on Xilinx's Virtex-II PRO FPGA and present several case studies and actual demonstration of a complete system from concept to implementation." @default.
- W2059092162 created "2016-06-24" @default.
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- W2059092162 date "2004-02-16" @default.
- W2059092162 modified "2023-09-28" @default.
- W2059092162 title "A demonstration of co-design and co-verification in a synchronous language" @default.
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- W2059092162 doi "https://doi.org/10.5555/968879.969122" @default.
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