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- W2059263268 abstract "We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-processors. The architecture is highly scalable, has high temporal throughput (80 MHz or more temporal frame samples/second, per sensor), and has excellent local interconnectivity. A single Xilinx Virtex-II xc2v2000 FPGA device circuit implementation is described for a highly selective first-order 2D infinite impulse response (IIR) broadband frequency-planar beam plane-wave filter, operating at a frame sample rate in excess of 80 MHz over a synchronously sampled linear sensor array consisting of 15 sensors and 15 A/D converters" @default.
- W2059263268 created "2016-06-24" @default.
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- W2059263268 date "2006-12-01" @default.
- W2059263268 modified "2023-10-16" @default.
- W2059263268 title "FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters" @default.
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- W2059263268 doi "https://doi.org/10.1109/apccas.2006.342528" @default.
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