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• W2061058895 abstract "A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm 2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit." @default.
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• W2061058895 date "2014-06-01" @default.
• W2061058895 modified "2023-09-30" @default.
• W2061058895 title "A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing" @default.
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• W2061058895 doi "https://doi.org/10.1109/iscas.2014.6865453" @default.
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