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- W2061418325 abstract "Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward scheme. However, this scheme requires large memory to store intermediate results. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding. The proposed scheme first chooses a limited number of variable-to-check messages, then the check-to-variable messages to all connected variable nodes are generated independently. Employing the proposed architecture, the area requirement of the check node processing for an (837, 726) NB-LDPC code over GF (25) can be reduced to 22.5% of that of the previous work with the same processing speed and error-correcting performance." @default.
- W2061418325 created "2016-06-24" @default.
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- W2061418325 date "2010-10-01" @default.
- W2061418325 modified "2023-10-07" @default.
- W2061418325 title "Reduced-complexity check node processing for non-binary LDPC decoding" @default.
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- W2061418325 doi "https://doi.org/10.1109/sips.2010.5624765" @default.
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