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- W2061421736 abstract "In this paper, design and optimization considerations for bulk gate-all-around nanowire MOSFETs have been investigated based on calibrated three-dimensional quantum correction numerical simulation. As device parasitical parameters play a crucial role in the optimization of overall performance of nanoscale bulk nanowire MOSFETs, we have placed great emphasis on projecting insights into the design of parasitic grooved-gate transistor and the source/drain (S/D) extension region. Furthermore, taking several important electrical parameters such as Vth, Ion, Ioff, subthreshold swing (Ss) and drain-induced barrier lowering (DIBL) as scaling criteria, the scaling of gate dielectric oxide (tox) and the diameter of nanowire (tsi) is discussed. The request for a high-k gate dielectric could be postponed due to the novel advanced structure, and there exists an optimal tsi for high performance application." @default.
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- W2061421736 date "2009-09-08" @default.
- W2061421736 modified "2023-09-24" @default.
- W2061421736 title "Design and optimization considerations for bulk gate-all-around nanowire MOSFETs" @default.
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- W2061421736 doi "https://doi.org/10.1088/0268-1242/24/10/105006" @default.
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