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W2061510074 abstract "A duty cycle detector based on time-to-digital conversion is presented. It combines the advantages of analogue (high accuracy and simplicity) and digital (digital output) duty cycle correctors in a simple and straightforward topology. Two identical circuits detect the high and low phases of the input clock and deliver two digital words. These two words are then sufficient to accurately estimate the input duty cycle. By using the same topology for both circuits, accuracy is affected only by mismatches between them. Designed in a bulk 28nm CMOS technology the proposed duty cycle detector achieves a maximum linearity error of 4% and a resolution of 0.5% over corners and an input duty cycle range of [20, 80]%." @default.
W2061510074 created "2016-06-24" @default.
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W2061510074 date "2013-02-01" @default.
W2061510074 modified "2023-09-25" @default.
W2061510074 title "Duty‐cycle detector based on time‐to‐digital conversion" @default.
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W2061510074 doi "https://doi.org/10.1049/el.2012.4276" @default.
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