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- W2061615893 abstract "The authors discuss throughput enhancement for pipelining and digital signal processing applications in a multiprocessor environment. A common objective in pipelining and digital signal processing is the repeated execution of the same computational job consisting of a set of computational operations with high throughput or sampling rates. For good performance and avoidance of internal conflicts, the concurrent computational operations of successive data sets of a computational job should be properly scheduled. Heuristic suboptimal scheduling algorithms are developed whose execution time is a polynomial function of the number of items to be scheduled. Insertion of delay is used as a basic tool for better utilization of hardware, thereby increasing the throughput. Rescheduled computational jobs are directed to architectures consisting of arbitrary number of processors. Simulation results are presented.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
- W2061615893 created "2016-06-24" @default.
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- W2061615893 date "1992-01-01" @default.
- W2061615893 modified "2023-09-26" @default.
- W2061615893 title "Throughput enhancement in multiprocessor architectures for pipelining and digital signal processing applications" @default.
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- W2061615893 doi "https://doi.org/10.1109/pccc.1992.200540" @default.
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