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- W2062917220 abstract "Through-silicon via technology is becoming inevitable to follow the increasing interconnect density required in today's logic products. But there are advantages to other markets as well: system-in-package solutions that integrate MEMS and ASIC chips have clearly different requirements, i.e. increased robustness against mechanical stress. Rather than targeting for ultra-thin silicon, they require standard wafer thicknesses. This article lines out some challenges in the implementation of a viable post-CMOS feedthrough technology in this domain." @default.
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- W2062917220 date "2006-12-01" @default.
- W2062917220 modified "2023-10-03" @default.
- W2062917220 title "Design rules for post-CMOS through silicon vias in an industrial environment" @default.
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- W2062917220 doi "https://doi.org/10.1109/eptc.2006.342687" @default.
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