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- W2063217670 abstract "Because of the increasing complexity of modern embedded systems, High-Level Synthesis (HLS) has gained momentum. Most HLS tools employ Control Data Flow Graph (CDFG) based approaches. An alternative route from C to RTL was presented in [1], where a CDFG based approach was augmented with a polyhedral process networkbased approach. This alternative route enables application of high-level transformations giving a significant increase in utilization of pipelined components, which positively affects throughput. However, increased pipeline utilization could be obtained only after manuallyselecting a set of transformations to apply, which is a non-trivial task.The main contribution of this paper is a reordering buffer that enablesautomatic improvement of pipeline utilization." @default.
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- W2063217670 date "2012-07-01" @default.
- W2063217670 modified "2023-10-05" @default.
- W2063217670 title "Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations" @default.
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- W2063217670 doi "https://doi.org/10.1109/asap.2012.23" @default.
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