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- W2063220919 abstract "Stream processors have emerged as a mainstream solution for computation intensive applications. This paper proposes a power-efficient network-on-chip (NoC) for multi-core stream processors, aiming at improving the communication performance and power consumption. In the proposed NoC, specific stream paths are proposed according to features of multi-core stream processing. Specific stream paths are constructed based on a packet-switched NoC, providing fast and power-efficient transmissions for stream communications. To support specific stream paths on the packet-switched NoC, the modified micro-architecture of the router is proposed with a negligible area overhead. A set of stream applications are exploited for evaluation. Experimental results show that, an average of 16.0% latency reduction and 35.9% power saving can be obtained." @default.
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- W2063220919 date "2013-10-01" @default.
- W2063220919 modified "2023-09-28" @default.
- W2063220919 title "A power-efficient network-on-chip for multi-core stream processors" @default.
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- W2063220919 doi "https://doi.org/10.1109/asicon.2013.6811833" @default.
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