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• W2065485025 abstract "Semiconductor testing, aimed at detecting manufacturing defects and marginalities, should be able to screen out fabrication artifacts that affect immediate as well as future mission-mode device performance. While a large amount of resources are dedicated towards catastrophic fault detection, parametric fault detection is an increasingly important research area. Parametric faults marginally affect device performance and may affect functionality in prolonged field use. In this work, Circuit-under-test (CUT) static bias current is monitored in order to identify catastrophic as well as parametric defects. Any active circuit requires a deterministic amount of DC bias current which may vary outside the specifications when faults exist within the circuit. We propose a process-voltage-temperature (PVT) compensated current measurement built-in-self-test (BIST) scheme, which can be used for sub-system level/circuit-level bias current measurements. The BIST scheme provides better accessibility to internal blocks and enables isolated parametric testing. Process independence due to calibration makes it feasible for commercial implementation in Systems on a Chip (SoCs). Our BIST scheme is compatible with very-low-cost automatic test equipment (VLC-ATE), and can be used for detailed parametric testing in the production environment." @default.
• W2065485025 created "2016-06-24" @default.
• W2065485025 creator A5068070739 @default.
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• W2065485025 date "2010-05-01" @default.
• W2065485025 modified "2023-09-26" @default.
• W2065485025 title "Calibration-enabled scalable built-in current sensor compatible with very low cost ATE" @default.
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• W2065485025 doi "https://doi.org/10.1109/etsym.2010.5512770" @default.
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