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- W2065994992 abstract "A fast-locked all-digital phase-locked loop (PLL) with supply noise suppression is presented. The analysis and design of this all-digital PLL is presented. While the supply noise exits, the loop bandwidth of this all-digital PLL is dynamically adjusted to suppress the jitter. This all-digital PLL is fabricated in a 0.18um CMOS process. It achieves the locked time of 22.5us and 78us with and without the fast-locked circuit, respectively. The measured peak-to-peak jitter and rms jitter are 38.9ps and 5.9ps, respectively, at 1.25GHz." @default.
- W2065994992 created "2016-06-24" @default.
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- W2065994992 date "2010-04-01" @default.
- W2065994992 modified "2023-09-24" @default.
- W2065994992 title "A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression" @default.
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- W2065994992 doi "https://doi.org/10.1109/vdat.2010.5496733" @default.
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