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- W2067462021 abstract "In this paper, a novel antilogarithmic converter using four-region piecewise-linear approximation is proposed. The proposed technique provides a lower error and area-efficient hardware implementation for antilogarithmic converter with 0.5681% of percent error range, which can outperform previously proposed methods with four-region and six-region schemes. The delay and area of the hardware implementation is 10ns and 6,639 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , respectively using 0.18 μm TSMC process." @default.
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- W2067462021 date "2012-12-01" @default.
- W2067462021 modified "2023-10-16" @default.
- W2067462021 title "A lower error antilogarithmic converter using novel four-region piecewise-linear approximation" @default.
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- W2067462021 doi "https://doi.org/10.1109/apccas.2012.6419083" @default.
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