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- W2068051287 abstract "A multidrain NMOS circuit configuration (MD) is studied and its advantages over the conventional pull-up pull-down (PUD) configuration are discussed. These include efficient use of silicon area, less sensitivity to interconnections, less delay times, a controlled value of logic swing which is independent of V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</inf> , and the possibility of integrating into a stacked structure where the load does not consume silicon real state. The MD and the PUD configurations are compatible and the latter is used where a large fan-out is required." @default.
- W2068051287 created "2016-06-24" @default.
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- W2068051287 date "1982-04-01" @default.
- W2068051287 modified "2023-09-23" @default.
- W2068051287 title "Multidrain NMOS for VLSI logic design" @default.
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- W2068051287 doi "https://doi.org/10.1109/t-ed.1982.20777" @default.
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