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- W2069041760 abstract "This paper presents architectures for comparator trees capable of finding the minimum value of a large number of inputs. Such circuits are of general applicability although the intended application for which the circuits were designed is the winner-take-all function of a digital implementation of a neural network based on the self organising map. Mechanisms for reducing delay based on look-ahead logic within individual comparators and mechanisms based on multiplexor architectures of a comparator are compared for both propagation delay and area." @default.
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- W2069041760 date "2004-12-01" @default.
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- W2069041760 title "Comparator trees for winner-take-all circuits" @default.
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- W2069041760 doi "https://doi.org/10.1016/j.neucom.2004.05.002" @default.
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