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- W2069199544 abstract "Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing." @default.
- W2069199544 created "2016-06-24" @default.
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- W2069199544 date "2004-01-01" @default.
- W2069199544 modified "2023-09-23" @default.
- W2069199544 title "Low-power dual V th pseudo dual V dd domino circuits" @default.
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- W2069199544 doi "https://doi.org/10.1145/1016568.1016640" @default.
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