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- W2069631845 abstract "We propose a method to analysis the delay of the sub-path on fabricated chips by the several path-delay tests. In recent years, the process variation causes the timing faults. To detect the faults, the path-delay test is one of the most promising methods. The path-delay test checks whether the signals along the target paths in fabricated LSIs are propagated under the specified frequency. In this paper, we propose a method to analysis the delay value of the paths with path-delay tests. The proposed method consists of 1) path-delay tests for several paths, 2) estimation of the sub-path of the testing paths, and 3) expansion of the remaining path according to the resultant estimations. We confirm that our proposed method calculates the delay with about 0.05% errors empirically." @default.
- W2069631845 created "2016-06-24" @default.
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- W2069631845 date "2010-05-01" @default.
- W2069631845 modified "2023-09-23" @default.
- W2069631845 title "Delay analysis of sub-path on fabricated chips by several path-delay tests" @default.
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- W2069631845 doi "https://doi.org/10.1109/iscas.2010.5537436" @default.
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