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- W2070505984 abstract "The design of a new, fast systolic stack is systematically carried out by traversing the qualitatively distinct levels of representation of the VLSI design hierarchy. Included in the overall VLSI design process is a formal verification of design correctness, circuit design and layout, as well as a performance analysis of area, time, clock frequency and design extendability. The novel systolic network has been obtained from a known network by applying a transformation technique based on packing and unpacking data elements into packets; the packet approach is used as a timing optimisation technique to eliminate the slowness of the known network." @default.
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- W2070505984 date "1988-01-01" @default.
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- W2070505984 title "Traversing the VLSI design hierarchy for a new, fast systolic stack" @default.
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- W2070505984 doi "https://doi.org/10.1049/ip-e.1988.0004" @default.
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