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• W2070916037 abstract "We propose an analog fuzzy logic controller chip structure in 1.2μm CMOS technology. It employs a new architecture for fuzzifier circuit that generates membership functions with a very suitable range and precision. These membership functions are simply tunable by setting some voltages on IC pins. Input has three membership functions and output is five singleton membership functions. Also, a novel defuzzifier circuit is used which occupies a small chip area. The controller is tested for two inputs, one output, and nine tunable fuzzy rules. The proposed architecture has an operation speed of 6.25MFLIPS (6.25×106 fuzzy logic inference per second) and power consumption of 16.3mW. The whole chip area is less than 0.7mm2 which is very small. Simulation tests show a good functionality of controller in response to some inputs to confirm the success of the design. The application of the system to the synthesis of a second-order system in a feedback loop is also considered." @default.
• W2070916037 created "2016-06-24" @default.
• W2070916037 creator A5035961114 @default.
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• W2070916037 date "2002-12-01" @default.
• W2070916037 modified "2023-10-04" @default.
• W2070916037 title "Design of an analog CMOS fuzzy logic controller chip" @default.
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• W2070916037 doi "https://doi.org/10.1016/s0165-0114(02)00062-3" @default.
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