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- W2071245558 abstract "According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> and P <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> diffusion and N <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> -doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</inf> layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</inf> layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</inf> layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA." @default.
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- W2071245558 title "Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies" @default.
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- W2071245558 doi "https://doi.org/10.1109/t-ed.1985.21928" @default.
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