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• W2071549228 abstract "The mounting issues of decreased yield and reliability from nanoscale integrated circuit (IC) processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes and are a major concern to the long-term reliability of safety-critical systems in aerospace and automotive applications. Common semiconductor failure modes include, among others, time-dependent dielectric breakdown (TDDB), hot carrier injection (BCI) damage, and negative bias temperature instability (NBTI). Die-level prognostic test structures can detect and help mitigate untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process-aware design for improved yields. This tutorial addresses concepts of in-situ test structures as a solution to product yield enhancement, process reliability qualification and reliability monitoring throughout the lifetime of the product and include practical application examples." @default.
• W2071549228 created "2016-06-24" @default.
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• W2071549228 date "2013-05-01" @default.
• W2071549228 modified "2023-09-26" @default.
• W2071549228 title "Semiconductor failure modes and mitigation for critical systems embedded tutorial" @default.
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• W2071549228 doi "https://doi.org/10.1109/ets.2013.6569369" @default.
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