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• W2071761885 abstract "This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V." @default.
• W2071761885 created "2016-06-24" @default.
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• W2071761885 date "2001-01-01" @default.
• W2071761885 modified "2023-10-09" @default.
• W2071761885 title "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input" @default.
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• W2071761885 doi "https://doi.org/10.1109/4.972143" @default.
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