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- W2072222013 abstract "This paper describes the circuit design of a programmable logic array chip using four-phase dynamic circuits, operating at a nominal cycle time of 230 nanoseconds. Bootstrap circuit techniques are used to obtain high function and performance by satisfying some special requirements of PLA designs. These include a simple means for two-bit partitioning of the data inputs, a noninverting buffer circuit between precharged arrays, and a fast, compact on-chip driver for heavily loaded arrays. Multiphase clocking enables the use of master/slave type JK flip-flops with minimum circuitry and power dissipation. A polarity hold function is provided at the outputs to allow interfacing the dynamic design to static output circuits." @default.
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- W2072222013 date "1975-07-01" @default.
- W2072222013 modified "2023-09-26" @default.
- W2072222013 title "High-Speed Dynamic Programmable Logic Array Chip" @default.
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- W2072222013 doi "https://doi.org/10.1147/rd.194.0379" @default.
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