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- W2072753410 abstract "This paper presents a clock generator based on multiplying delay-locked loop (MDLL). With the aid of the frequency detector and the improved select logic circuitry, the clock generator can perform the lock-in process and the edge-selecting function correctly. It also provides the capability of the frequency switching like the conventional PLL-based clock generators without any external control signal. The test chip is designed and fabricated in TSMC 0.18 µm CMOS process. The core circuitry occupies an area of 0.06 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and consumes the power of 22.4 mW at the output frequency of 1.19 GHz. The measured peak-peak jitter is 19.2ps." @default.
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- W2072753410 date "2014-09-01" @default.
- W2072753410 modified "2023-10-18" @default.
- W2072753410 title "A clock generator based on multiplying delay-locked loop" @default.
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- W2072753410 doi "https://doi.org/10.1109/socc.2014.6948907" @default.
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