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- W2073199959 abstract "In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K ≥ 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z×Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations." @default.
- W2073199959 created "2016-06-24" @default.
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- W2073199959 date "2013-10-01" @default.
- W2073199959 modified "2023-09-27" @default.
- W2073199959 title "VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight" @default.
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- W2073199959 doi "https://doi.org/10.1109/tvlsi.2012.2220388" @default.
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