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- W2073260590 abstract "For thin-film transistor (TFT) characterization and simulation, accurate knowledge of the effective channel width ( <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$W_{rm EFF}$</tex></formula> ) and effective channel length ( <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$L_{rm EFF}$</tex></formula> ) is required, particularly in narrow and/or short devices, where small dimensional variations may result in large overestimation/underestimation of device parameters. Although a substantial amount of research has been done to determine <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$L_{rm EFF}$</tex></formula> , there is very little work presented regarding <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$W_{rm EFF}$</tex></formula> . Here, we report a design-related existence of current leakage paths along the channel edges in inverted staggered TFT structures. Applied here for the case of amorphous-silicon- and amorphous-oxide-semiconductor-based TFTs, a model is developed to investigate the edge effect from a series of TFTs with various channel widths ( <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$W$</tex></formula> ). <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex Notation=TeX>$W_{rm EFF}$</tex></formula> is found to be larger than the designed <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$W$ </tex></formula> , resulting in an overestimation of the extracted TFT parameters such as the field-effect mobility. It is concluded that a preferred TFT design consists of source and drain electrodes that extend over the active area along the <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$W$</tex></formula> direction to minimize the edge effects and, hence, improve the accuracy of the extracted TFT parameters." @default.
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- W2073260590 date "2012-09-01" @default.
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- W2073260590 title "Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors" @default.
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- W2073260590 doi "https://doi.org/10.1109/ted.2012.2205258" @default.
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