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- W2073379454 abstract "A simple and high speed adder architecture is presented in this paper. This adder uses pass transistor pairs to make a fast CMOS carry chain as used by the Manchester carry chain technique. It uses less hardware, and is faster than conventional ripple-carry adders. It is also significantly faster than the sign-select adder recently described by Srinivas et al. for word lengths less than or equal to 8, and is slightly faster than this adder for word lengths greater than 8. The structure, however, is simpler and more regular. This adder is well suited for VLSI implementation, and provides a useful trade-off between speed and complexity." @default.
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- W2073379454 date "1993-10-01" @default.
- W2073379454 modified "2023-10-14" @default.
- W2073379454 title "A simple and high speed CMOS carry chain adder architecture" @default.
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- W2073379454 doi "https://doi.org/10.1080/00207219308907152" @default.
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