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• W2073778925 abstract "DDR3 memory interface (I/F) with single-end signals is very sensitive to external environments, such as chip package type and system board design. In order to guarantee the system performance, IP providers often define the package and PCB design constraints to reduce product risks [1]. These design constraints may increase the package size and DDR3 PCB area to cost, increasing the whole system cost. Therefore, our DDR3 memory I/F design addresses this problem, relaxing the external environment requirements, especially relating to power integrity, and achieves 2.667Gb/s operation in a wirebond package and singleside mounted PCB. The difference between double-side and single-side mounted PCB is shown in Fig. 26.6.1. The capacitor on the PCB cannot be mounted directly near the SOC on the back side of PCB. This external environment increases the distance of the current return loop and also increases the inductance of power decouple capacitance equivalently." @default.
• W2073778925 created "2016-06-24" @default.
• W2073778925 creator A5011644287 @default.
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• W2073778925 date "2014-02-01" @default.
• W2073778925 modified "2023-09-24" @default.
• W2073778925 title "26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB" @default.
• W2073778925 cites W2080418535 @default.
• W2073778925 doi "https://doi.org/10.1109/isscc.2014.6757508" @default.
• W2073778925 hasPublicationYear "2014" @default.
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