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- W2074129723 abstract "This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm." @default.
- W2074129723 created "2016-06-24" @default.
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- W2074129723 date "2012-12-01" @default.
- W2074129723 modified "2023-10-12" @default.
- W2074129723 title "Low-power high-speed dual-modulus prescaler for Gb/s applications" @default.
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- W2074129723 doi "https://doi.org/10.1109/apccas.2012.6419020" @default.
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