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- W2074324585 abstract "This article presents a UWB receiver, which is made by the chips designed by our group in SMIC0.18um process, This receiver was verified by the measurement, With the help of FPGA it can synthesis 2.8G~3.98GHz LO frequency by changing the PLL and reference frequency, with reference frequency 21MHz, division ratio 1/160, it can be locked at 3.36GHz with the phase noise of −83dBc/Hz, the internal Digital VGA could be digitally controlled by FPGA with 30dB tuning range. Though Chip scope verification, This receiver can demodulate 500MHz Bandwidth signal without error bit rate by connected the receiver and transmitter with RF line return loss of 40dB, the power consumption of this receiver is 60mW." @default.
- W2074324585 created "2016-06-24" @default.
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- W2074324585 date "2010-05-01" @default.
- W2074324585 modified "2023-09-27" @default.
- W2074324585 title "A UWB down convert circuit and measurement" @default.
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- W2074324585 doi "https://doi.org/10.1109/icmmt.2010.5524741" @default.
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