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- W2074362038 abstract "The design and implementation in a 1.2 V, 130 nm CMOS technology of a parallel continuous-time ΣΔ modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation over a signal bandwidth of 528 MHz, with a 62.3 mW power consumption." @default.
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- W2074362038 date "2012-04-01" @default.
- W2074362038 modified "2023-09-23" @default.
- W2074362038 title "A 1.2V, 130nm CMOS parallel continuous-time ADC for OFDM UWB receivers" @default.
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- W2074362038 doi "https://doi.org/10.1016/j.mejo.2012.01.010" @default.
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