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- W2074457055 abstract "Testing of embedded systems, operating in the real environment, is generally performed by using an industrial test bench that stimulates the system through sensors and human-machine interfaces. The test bench provides the engineers with a set of tools for reproducing the environmental conditions which may affect the system. On the contrary, a different approach is adopted at the early stages of the design flow, when system level languages, like SystemC, are used to describe the functionality of the design. At this level, stimuli for testing the design are traditionally generated in a random or statistical way, which makes more difficult to capture well-specific behaviors of the considered environment, thus decreasing the effectiveness and the efficiency of the verification. This is particularly evident for dynamic assertion-based verification where, to avoid vacuous passes of assertions, stimuli must reflect specific scenarios to activate the assertions." @default.
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- W2074457055 date "2012-10-07" @default.
- W2074457055 modified "2023-10-18" @default.
- W2074457055 title "A testbench specification language for SystemC verification" @default.
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- W2074457055 doi "https://doi.org/10.1145/2380445.2380499" @default.
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