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- W2074667675 abstract "In this paper we present vertical tunnel diodes and tunnel FETs (TFETs) based on III-V-Si nanowire heterojunctions. We experimentally demonstrate InAs-Si Esaki tunnel diodes with record high currents of 6 MA/cm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> at 0.5 V in reverse bias. Furthermore, we have fabricated vertical InAs-Si nanowire TFETs with gate-all-around architecture and high-k dielectrics. The InAs-Si combination allows achieving high I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>off</sub> ratios above 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>6</sup> , with I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</sub> of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec over three decades. The achieved improvements can be attributed to increased nanowire doping and Ni alloying of the top contact. The results indicate the benefits of the InAs-Si material system combining the possibility of achieving high I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</sub> with high I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>off</sub> ratio." @default.
- W2074667675 created "2016-06-24" @default.
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- W2074667675 date "2012-12-01" @default.
- W2074667675 modified "2023-09-27" @default.
- W2074667675 title "InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs" @default.
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- W2074667675 doi "https://doi.org/10.1109/iedm.2012.6479056" @default.
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