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- W2076262257 abstract "A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 10 5 cycles and a data retention time of at least 10 years." @default.
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- W2076262257 date "2007-12-01" @default.
- W2076262257 modified "2023-10-17" @default.
- W2076262257 title "Reverse programmed SONOS memory technique for 0.18μm embedded utilization" @default.
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- W2076262257 doi "https://doi.org/10.1016/s1007-0214(07)70183-9" @default.
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