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- W2076289989 abstract "Robustness of domino circuit degrades with the downscaling of the device as leakage power increased. In this paper, we proposed different domino logic styles which improve the performance and also is capable of providing static output in the evaluation phase. According to the simulations in cadence virtuoso 180nm CMOS process, the proposed circuit shows the improvement of up to 50% compared to conventional domino logic circuits." @default.
- W2076289989 created "2016-06-24" @default.
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- W2076289989 date "2013-04-01" @default.
- W2076289989 modified "2023-10-16" @default.
- W2076289989 title "New domino logic designs for static outputs in evaluation phase for high frequency inputs" @default.
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- W2076289989 doi "https://doi.org/10.1109/sces.2013.6547515" @default.
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