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• W2076300899 abstract "A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is - 82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions." @default.
• W2076300899 created "2016-06-24" @default.
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• W2076300899 date "2012-05-01" @default.
• W2076300899 modified "2023-09-25" @default.
• W2076300899 title "A 130-nm CMOS 100-Hz–6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver" @default.
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• W2076300899 doi "https://doi.org/10.1109/tmtt.2012.2190091" @default.
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