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- W2076306725 abstract "Modular addition is a widely used operation in Residue Number System applications. Specific sets of moduli allow fast RNS operations such as binary conversions and multiplications. Most of them use modulo 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> - 1 and 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> + 1 additions. This paper presents four fast and small architectures for these specific moduli targeting modern FPGAs with fast carry chains. The use of this arithmetic dedicated feature allows fast and small modular adders. Our modulo 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> - 1 adders have a single zero representation. Our modulo 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> +1 adders are designed for binary and diminished-one representation with and without zero value management." @default.
- W2076306725 created "2016-06-24" @default.
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- W2076306725 date "2013-11-01" @default.
- W2076306725 modified "2023-09-26" @default.
- W2076306725 title "Fast modulo 2<sup>n</sup>−1 and 2<sup>n</sup>;1 adder using carry-chain on FPGA" @default.
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- W2076306725 doi "https://doi.org/10.1109/acssc.2013.6810475" @default.
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