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• W207639384 abstract "In this paper we experimentally explore the gate length scaling effects that related to the abrupt degradation of electrostatic discharge (ESD) robustness for ultra-thin body silicon on insulator (SOI) devices and integrated circuits (ICs). It is found that, for the ultra-thin body SOI, the ESD protection devices fail when the gate length of protection devices is smaller than the 0.18 micron meter (um). Taking the effects into consideration, it is believed that optimizations among the device profiles, geometries, and the protection efficiency should be done simultaneously for high performance VLSI circuit design, in particular for modern system-on-chip (SoC). This observation is very useful in both the nano-scale CMOS fabrication technology and VLSI circuit design." @default.
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• W207639384 date "2004-03-07" @default.
• W207639384 modified "2023-09-22" @default.
• W207639384 title "Gate Length Scaling Effects in ESD Protection Ultrathin Body SOI Devices" @default.
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