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- W2076474846 abstract "High conductivity gate electrode structures of sheet resistance ≲3 Ω/⧠ have been fabricated using a 2500 A (nominal) TaSi2 layer on 4500 A thick phosphorus doped polycrystalline silicon films. The TaSi2 layer was formed by cosputter depositing Ta and Si, using magnetron sources, and sintering in H2 at 900°C for 30 min. The composite structure was patterned using a CF4–O2 plasma etch process. The use of this structure has been compared directly with polycrystalline silicon gates in experiments using CMOS and NMOS devices. Device parameters, with the exception of a slight perturbation of VT for the CMOS devices, have been virtually identical for both types of gate electrode. Device yields are not affected by incorporating the TaSi2 layer. Device parameters show a tighter distribution probably due to the more uniform sheet resistance of the composite TaSi2/polycrystalline silicon layer." @default.
- W2076474846 created "2016-06-24" @default.
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- W2076474846 date "1981-03-01" @default.
- W2076474846 modified "2023-09-29" @default.
- W2076474846 title "Tantalum silicide/polycrystalline silicon—High conductivity gates for CMOS LSI applications" @default.
- W2076474846 doi "https://doi.org/10.1116/1.570756" @default.
- W2076474846 hasPublicationYear "1981" @default.
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