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- W2077157218 abstract "In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program.In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark." @default.
- W2077157218 created "2016-06-24" @default.
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- W2077157218 date "2002-01-01" @default.
- W2077157218 modified "2023-09-28" @default.
- W2077157218 title "Efficient architecture/compiler co-exploration for ASIPs" @default.
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- W2077157218 doi "https://doi.org/10.1145/581630.581635" @default.
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