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• W2078339735 abstract "Excellent performance (995 muA/mum at I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>off</sub> =94 n A/mum and V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> =lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</sub> variability is shown to explain this dependence upon fin width and gate length." @default.
• W2078339735 created "2016-06-24" @default.
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• W2078339735 date "2007-12-01" @default.
• W2078339735 modified "2023-10-02" @default.
• W2078339735 title "Gatestacks for scalable high-performance FinFETs" @default.
• W2078339735 doi "https://doi.org/10.1109/iedm.2007.4419037" @default.
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