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- W2078442861 abstract "SRAMs occupy a large amount of area in modern system on chip circuits. With the growing trend of device scaling in deep sub-micron technologies, the 6T SRAM write operation is more vulnerable than the read operation from a failure standpoint. In order to make the SRAMs operate correctly, we must design them with some guard band above the minimum operating voltage (V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>MIN</inf> ) by designing for the worst case. In this paper, we investigate a reverse write assist circuit scheme that enables the tracking of SRAM write V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>MIN</inf> by using canary SRAM bitcells to track dynamic voltage, temperature fluctuations and aging effects. This circuit ultimately allows us to lower the write V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>MIN</inf> below the worst case corner (SF_85C) V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>MIN</inf> , which saves a minimum of 30.7% energy per cycle at the SS_85C, and a maximum of 51.5% energy per cycle at the FS_85C corner." @default.
- W2078442861 created "2016-06-24" @default.
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- W2078442861 date "2014-03-01" @default.
- W2078442861 modified "2023-10-18" @default.
- W2078442861 title "A reverse write assist circuit for SRAM dynamic write V<inf>MIN</inf> tracking using canary SRAMs" @default.
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- W2078442861 doi "https://doi.org/10.1109/isqed.2014.6783299" @default.
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