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- W2078484802 abstract "Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average." @default.
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- W2078484802 date "2008-04-01" @default.
- W2078484802 modified "2023-09-23" @default.
- W2078484802 title "A Low-Power Instruction Issue Queue for Microprocessors" @default.
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- W2078484802 doi "https://doi.org/10.1093/ietele/e91-c.4.400" @default.
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