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- W2078690603 abstract "SIMD instruction cache (or I-cache) is proposed to remedy a heretofore un-compensated instruction delivery rate limitation of SIMD computers. This paper introduces the concept of SIMD I-cache and sketches the I-cache design space. On the basis of throughput using chip area as a hardware cost constraint, detailed evaluations of simple I-cache variants for a diverse set of sample problems are presented. Simple I-cache variants occupy negligible area in chips while providing significant speedups, even for problems ordinarily thought to be inherently communication-bound. These results suggest that I-cached SIMD computers exhibit the highest throughput of any multiprocessors for scalable data-parallel problems." @default.
- W2078690603 created "2016-06-24" @default.
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- W2078690603 date "1994-01-01" @default.
- W2078690603 modified "2023-09-27" @default.
- W2078690603 title "SIMD instruction cache" @default.
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- W2078690603 doi "https://doi.org/10.1145/181014.181034" @default.
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